This application claims the benefit of priority under 35 U.S.C. xc2xa7 119 to Japanese Patent Application No. 2001-39122 filed on Feb. 15, 2001, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device which dynamically stores data with using a channel body of a transistor as a storage node.
2. Related Background Art
In a related DRAM, a memory cell is composed of an MOS transistor and a capacitor. The scale-down of the DRAM has been remarkably advanced by the adoption of a trench capacitor structure and a stacked capacitor structure. At present, the cell size of a unit memory cell is scaled down to an area of 2 Fxc3x974 F=8 F2, where F is a minimum feature size. Namely, the minimum feature size F decreases with the advance of generation, and when the cell size is generally taken to be xcex1F2, a coefficient xcex1 also decreases with the advance of generation. Thus, at the present of F=0.18 xcexcm, xcex1=8 is realized.
In order to hereafter secure the trend of cell size or chip size which is the same as before, it is demanded to satisfy xcex1 less than 8 in F less than 0.18 xcexcm and further satisfy xcex1 less than 6 in F less than 0.13 xcexcm, and together with microfabrication, the formation of cell size of the possible small area becomes a large problem. Accordingly, various proposals for decreasing the size of the one memory cell with the one transistor and one capacitor to 6F2 or 4F2 are made. However, practical use is not easy since there are a technical difficulty that the transistor has to be a vertical type, a problem that electric interference between adjacent memory cells increases, and in addition difficulties in terms of manufacturing technology including fabrication, film formation, and the like.
On the other hand, some proposals for a DRAM in which a memory cell is composed of one transistor without using a capacitor are made as mentioned below.
(1) JOHN E. LEISS et al, xe2x80x9cdRAM Design Using the Taper-Isolated Dynamic Cellxe2x80x9d (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 4, APRIL 1982, pp707-714)
(2) Japanese Patent Laid-open Publication No. H3-171768
(3) Marnix R. Tack et al, xe2x80x9cThe Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperaturesxe2x80x9d (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL, 37, MAY, 1990, pp1373-1382)
(4) Hsing-jen Wann et al, xe2x80x9cA Capacitorless DRAM Cell on SOI Substratexe2x80x9d (IEDM93, pp635-638)
A memory cell in the document (1) is composed of MOS transistors, each of which has a buried channel structure. Charge and discharge to/from a surface inversion layer is performed using a parasitic transistor formed at a taper portion of an element isolation insulating film to perform binary storage.
A memory cell in the document (2) uses MOS transistors which are well-isolated from each other and uses a threshold voltage of the MOS transistor fixed by a well potential as binary data.
A memory cell in the document (3) is composed of MOS transistors on an SOI substrate. A large negative voltage is applied from the SOI substrate side, and by utilizing accumulation of holes in an oxide film of a silicon layer and an interface, binary storage is performed by emitting and injecting these holes.
A memory cell in the document (4) is composed of MOS transistors on an SOI substrate. The MOS transistor is one in terms of structure, but here a structure, in which a reverse conduction-type layer is formed on top of the surface of a drain diffusion region, whereby a P-MOS transistor for write and an N-MOS transistor for read are substantially combined integrally, is adopted. With a substrate region of the N-MOS transistor as a floating node, binary data are stored by its potential.
However, in the document (1), the structure is complicated and the parasitic transistor is used, whereby there is a disadvantage in the controllability of its characteristic. In the document (2), the structure is simple, but it is necessary to control potential by connecting both a drain and a source of the transistor to a signal line. Moreover, the cell size is large and rewrite bit by bit is impossible because of the well isolation. In the document (3), a potential control from the SOI substrate side is needed, and hence the rewrite bit by bit is impossible, whereby there is a difficulty in controllability. In the document (4), a special transistor structure is needed, and the memory cell requires a word line, a write bit line, a read bit line, and a purge line, whereby the number of signal lines increases.
According to one aspect of the present invention, a semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors comprising:
a semiconductor layer;
a source region formed in the semiconductor layer;
a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a body region in a floating state; and
a first gate which forms a channel in the body region;
a second gate formed in addition to the first gate, a potential of the second gate being fixed so as to control a potential of the body region by a capacitive coupling;
wherein the MIS transistor has a first data state in which the body region has a first potential set by impact ionization generated near a drain junction and a second data state in which the body region has a second potential set by a forward current flowing through the drain junction.